As a semiconductor device including a multi-finger type FET (Field Effect Transistor) of which a source electrode, a gate electrode and a drain electrode are formed of a plurality of fingers respectively, a semiconductor device described in Patent Document 1 is well known.    Patent Document 1: JP, 11-87367, A.
FIG. 5 is a figure for explaining an electrode structure of a semiconductor device of the Patent Document 1.
That is, in this semiconductor device, as shown in FIG. 5(a), a gate finger electrode 2, a source finger electrode 3, and a drain finger electrode 4 are disposed so that they may engage mutually in the central part mostly on a rectangular substrate 53. That is, it is disposed so that a relation that the gate finger electrode 2 is placed between the source finger electrode 3 and the drain finger electrode 4 may be repeated. A gate pad 50 to which the gate finger electrode 2 is connected, and a source pad 51 to which the source finger electrode 3 is connected are disposed by turns along with one side (the lower side of the figure) of the substrate 53. And, a drain pad 52 to which the drain finger electrode 4 is connected is disposed along with a side (surface of the figure) to which the substrate 53 faces.
As shown in FIG. 5(b), as for the substrate 53, a metal ground plate 54 as a ground is formed on the backside. An input side substrate 55 and an output side substrate 56 with which an input side matching circuit and an output side matching circuit (not shown) are formed on the surface, respectively are provided in an input side and an output side of the substrate 53. The ground plate 54 is formed so that the part may be exposed on the substrate surface between the input side substrate 55 and the substrate 53.
The source pad 51 is bonded to an exposed part 58 of the ground plate 54 with a wire 57, and, accordingly the source electrode is grounded. Moreover, the gate pad 50 is connected to the matching circuit for the input on the input side substrate 55 through a wire 59, and the drain pad 52 is connected to the matching circuit for the output on the output side substrate 56 through wires 60 and 61.
On the other hand, in such multi-finger type FET, a device described in Patent Document 2 is conventionally known as a semiconductor device of structure where the source pad is grounded through a via hole (VIA).    Patent documents 2: JP, 11-283996, A.
In the conventional semiconductor device shown in FIG. 5 mentioned above, since the wire 59 which connects a matching circuit and the gate pad 50 for the input on the input side substrate 55 is connected ranging over the exposed part 58 of the ground plate, only worth equivalent to width of the exposed part 58 requires longer wire length. As a result, the input inductance of the wire becomes longer, and therefore there is a fault of reducing the resonance frequency. It becomes impossible for this reason, to compose the matching circuit for operation on high frequency.
Furthermore, a part with which the gate bus-line and the finger part of the source electrode overlap, i.e., parasitic capacitance by an overlay 62, has great influence on gain of the FET.
FIG. 6 is a figure for explaining an electrode structure of the semiconductor device of Patent Document 2. As this semiconductor device is shown in FIG. 6, arrangement and structure of a gate pad 50 and a source pad 51 differ from the semiconductor device shown in FIG. 5. That is, in the semiconductor device shown in FIG. 6, the gate pad 50 and the source pad 51 are disposed by two rows along the lower side of a substrate 53. The source pad 51 is connected to a metal ground plate (not shown) provided in the backside of the substrate 53 through a via hole 63. The gate pad 50 is shifted along the lower side of the substrate 53, and is placed so as to be placed for the source pad 51 on a position between them. The gate pad 50 is connected to each gate finger electrode 2 through a gate drawing line 65, which passes through between the adjoining source pads 51, respectively. In addition, in FIG. 6, the same reference numeral is attached to a part corresponding to a component of the semiconductor device shown in FIG. 5.
In the conventional device shown in FIG. 6, since between the gate pad 50 and the gate electrode 2 is connected by the gate drawing line 65, after all, a wire length of the gate becomes long and the input inductance becomes large.
Then, an object of the present invention is to provide an FET having small input inductance, in view of the above-mentioned subject.